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[VHDL-FPGA-Verilog] CRC_module_of_FPGA

Description: 利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能-use VHDL to prepare a crc function of the module, which can be downloaded to the FPGA functions
Platform: | Size: 3072 | Author: 黎飞飞 | Hits:

[VHDL-FPGA-Verilog] CRC_VHDL

Description: 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
Platform: | Size: 204800 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] crc_32_16

Description: crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Platform: | Size: 296960 | Author: likj | Hits:

[Other] crc_pkg

Description: VHDL语言实现的CRC校验，函数形式，包括CRC4,CRC8,CRC16和CRC32-VHDL language to achieve the CRC checksum, function forms, including CRC4, CRC8, CRC16 and CRC32
Platform: | Size: 2048 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Platform: | Size: 163840 | Author: 夏杰 | Hits:

[Crack Hack] crc

Description: 此源代码实现了CRC5和CRC16的校验以及校验码的产生，可以直接用于RFID标签数字电路。-This source code CRC5 and realize the CRC16 checksum and the emergence of parity-check codes, RFID tags can be directly used for digital circuits.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] ultimate_crc.tar

Description: VHDL语言实现的CRC码程序,可用于FPGA实现-VHDL language procedures realize the CRC code can be used to realize FPGA
Platform: | Size: 114688 | Author: 陈楚龙 | Hits:

[Communication] CRC16_D8.v

Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
Platform: | Size: 1024 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[VHDL-FPGA-Verilog] serial_crc

Description: VHDL源代码,资源多多共享,不懂的地方多多指教-VHDL source code, resources, a lot of sharing, do not know where the exhibitions
Platform: | Size: 1024 | Author: wangzhe | Hits:

[VHDL-FPGA-Verilog] parallel_crc

Description: VHDL源代码,资源多多共享,不懂的地方多多指教-VHDL source code, resources, a lot of sharing, do not know where the exhibitions
Platform: | Size: 1024 | Author: wangzhe | Hits:

[VHDL-FPGA-Verilog] crccode

Description: CRC循环冗余检验 Verilog 编码程序-CRC cyclic redundancy test Verilog coding procedures
Platform: | Size: 1024 | Author: yuanxiaonan | Hits:

[VHDL-FPGA-Verilog] CRC

Description: verilog 实现循环冗余校验 源代码-Cyclic Redundancy Check realize Verilog source code
Platform: | Size: 367616 | Author: 长空 | Hits:

[Program doc] CRC

Description: FPGA实现差错控制编码技术，非常不错的一篇毕业论文，很详细，推荐-FPGA realization of error control coding techniques, a very good dissertation, I am very detailed and recommended
Platform: | Size: 431104 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[VHDL-FPGA-Verilog] CRC_xapp562

Description: crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
Platform: | Size: 49152 | Author: lh | Hits:

[VHDL-FPGA-Verilog] crcm

Description: crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[VHDL-FPGA-Verilog] CRC16bits

Description: 16bit crc encoder ande demo
Platform: | Size: 167936 | Author: chen | Hits:

[Crack Hack] CRC

Description: 通过对于模2除法的研究 可以得到如下方法： 1． 把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2． 在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3． 如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4． 把滑块变量d往后滑动一位。 5． 循环步骤（3，4）11次。 6． 执行步骤3。 7． 得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:
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